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Abstract:

O bject matching and identification are the popular research in the field of computer vision . The methods are mainly based on feature matching . In many feature extraction algorithms, SIFT (Scale invariant feature transform) is considered to be one of the best algorithms. It maintains the robustness for image scalin g, r otation, deformation, and light changes. However, it require complex calculations and large amounts of memory that makes it difficult to achieve real-time.

In order to a chieve real time operations and reduce memory requirements, we propose a new SIFT h ardware architecture and improve the SIFT algorithm in this thesis . In the step of construct ing Gaussian pyramids, the original cascade operations is substituted by parallel operations. Although it increase the amount of calculations , we can reduce the amo unt of temporary memory and increase the speed. For the first octave images, we adapt a smaller scale space to simulate the high spatial frequency instead of upsampling image T he step of keypoint localization is replaced by appropriate threshold to filter out the bad extremum I n addition, the overall algorithm is based on segment which can be greatly reduced the internal memory in the design. We verified the hardware architecture on FPGA (Xi linx Artix7) and implemented by TSMC90nm process. Experimental re sults show that for an image with a resolution of 1280x720, the operating frequency can reach 1 5 2 MHz, t he processing speed can reach 3 5 .6 frames/s, and the internal memory requirement is 2 37 Mbits.

Hardware Architecture:

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